Integrated circuit (IC) devices typically include numerous transistors that are fabricated on, for example, silicon wafers. For a given power supply voltage, the electric field strength, e.g., the change in voltage per unit length, that these transistors are exposed to increases as the size of the transistors is reduced. The maximum electric field tolerance can be a limiting factor on the minimum transistor size of an IC device. For example, a typical maximum gate oxide field strength for a silicon dioxide gate is about 3 megavolts per centimeter. High electric fields inside a transistor can reduce the mean time to failure, and can destroy transistors of an IC device when an electric field exceeds the breakdown value for a given material in a transistor, such as the gate oxide in CMOS devices.
Until recently, 5V supplies were typically used to power digital IC devices. Recently, there has been a trend toward the use of 3.3V supplies that allow a reduction in the minimum transistor size in certain types of digital logic IC devices, including CMOS devices. These 3.3V digital logic devices must often be connected in a system to other IC devices that operate with 5V supplies, such as, for example, TTL devices. However, without protection, the electric field generated by such 5V TTL devices would exceed the breakdown value of the gate oxide in the transistors of the 3.3V devices. Therefore, an interface circuit is generally required to isolate the electric field of the 5V TTL devices from the transistors in the 3.3V IC devices.
Programmable logic devices (PLDs) are IC devices that typically include a plurality of logic elements and associated interconnect resources that are programmed by a user to implement user-defined logic operations (that is, a user's circuit design). PLDs are programmed using a personal computer or workstation and appropriate software. Therefore, unlike application specific integrated circuits (ASICs) that require a protracted layout process and an expensive fabrication process to implement a user's logic operation, a PLD may be utilized to implement the logic operation in a relatively quick and inexpensive manner.
FIG. 1 shows a portion of a field programmable gate array (FPGA) 100, which is one type of PLD that is sold with a 3.3V supply. Although greatly simplified, FPGA 100 is generally consistent with XC3000.TM. series FPGAs, which are produced by Xilinx, Inc. of San Jose, Calif. FPGA 100 includes an array of configurable function blocks (FBs) 110, input/output (I/O) blocks 120 surrounding the array of FBs 110, and programmable interconnect resources that include interconnect channels 130 (indicated by dashed lines) extending between the rows and columns of FBs 110. Each FB 110 includes configurable combinational circuitry and optional output registers, and conductive wires 115 that connect (via programmable elements, not shown) to the interconnect channels 130. All of the FBs 100 of an FPGA are typically identical. I/O circuits 120 are connected between an I/O pin 140 of FPGA 100 and the interconnect channels 130. Each I/O circuit 120 is programmable to transmit input signals from an associated I/O pin 140 to a selected FB 110, or to transmit output signals from an FB 110 to the associated I/O pin 140. The interconnect channels 130 comprise discrete wire segments that are linked by programmable elements to selectively form signal paths between the FBs 110 and I/O circuits 120. Specifically, the interconnect resources are programmable to selectively provide I/O-to-FB connections, FB-to-FB connections, and FB-to-I/O connections that are associated with a user's logic operation.
FIG. 2 is a simplified diagram showing a portion of a known I/O circuit 120(1). I/O circuit 120(1) receives output signals from FBs 110 via interconnect channels 130 on a DATA OUT line. The output signal is transmitted to an output circuit 121 that generates a pull-up signal D1 and a pull-down signal D2 that are used to generate a high or a low output signal at I/O pin 140(1). The pull-up signal is applied to the gate of P-channel pull-up transistor 122, and the pull-down signal D2 is applied to the gate of N-channel pull-down transistor 123. Pull-up transistor 122 has a source connected to Vcc (e.g., 3.3 volts), and a drain connected to I/O pin 140(1). Pull-down transistor 123 has a source connected to ground, and a drain connected to I/O pin 140(1). The voltage at the N-well (body) of pull-up transistor 122 is controlled by a well bias control circuit 124 (discussed below). A first diode 125 is connected between I/O pin 140(1) and the output terminal of well bias control circuit 124. A second diode 126 is connected between I/O pin 140(1) and a global Vtt bus 150 that extends around a periphery of the FPGA on which I/O circuit 120(1) is located. A bipolar ESD circuit 127 is provided between I/O pin 140(1) and ground. Finally, input signals applied to I/O pin 140(1) are transmitted out of I/O circuit 120(1) on a DATA IN line via a buffer 128 comprised of serially-connected inverters.
I/O circuit 120(1) operates in two modes: an output mode in which I/O pin 140(1) is used for transmitting output signals from the PLD, and an input mode in which I/O pin 140(1) is used for receiving input signals from an external source, and passing the input signals to the internal portions of the PLD. In the output mode, output circuit 121 receives output signals from the internal portions of the PLD on the DATA OUT line, and drives pull-up transistor 122 and pull-down transistor 123 to generate appropriate high or low output signals on output pin 140(1). In the input mode, output circuit 121 is placed in a tristate mode, thereby disconnecting the DATA OUT line from I/O pin 140(1). This disconnection allows input signals to pass unimpeded from I/O pin 140(1) through buffer 128 and into the PLD on the DATA IN line.
A 3.3V PLD can safely drive its own I/O pin when the I/O pin is being used for output. However, when the I/O pin of a 3.3V PLD is being driven by a neighboring 5V device (i.e., in the input mode), the 3.3V PLD must prevent the 5V signals from damaging the pull-up transistors of the I/O circuit. This damage control is accomplished in I/O circuit 120(1) using well bias control circuit 124 and diode 125, which connect the N-well of pull-up transistor 122 to Vcc (3.3V) during the output mode, and to I/O pin 140(1) in the input mode. Connecting the N-well to I/O pin 140(1) in the input mode allows input signals up to 5.5V input signals without creating a forward biased diode between the N-well of pull-up transistor 122 and Vcc, thereby preventing damage to the PLD.
In addition, I/O circuit 120(1) includes diode 126 that is connected between I/O pin 140(1) and a global Vtt bus 150 when PCI compliance is required. When the PLD is to be 5V tolerant, Vtt bus is left floating. When PCI compliance is desired, the Vtt bus is bonded via connection 160 to a special Vtt pad 170 that is tied to the 3.3V power supply. This connection protects the PLD by limiting the maximum voltage at I/O pin 140(1) that is common to the low and high voltage devices. When an external voltage is applied to I/O pin 140(1) that is sufficiently greater than the power supply voltage, diode 126 turns on and draws current.
A problem with I/O circuit 120(1) is that Vtt bus 150 takes up a significant amount of area, and typically must be bonded to several pins that could otherwise be used for I/O purposes. Vtt bus 150 extends around the entire periphery of a PLD, and must be wide enough to carry the significant currents that can be generated when PCI compliance is desired. Therefore, Vtt bus 150 takes up a significant amount of area that could otherwise be used for logic circuits. In addition, Vtt bus 150 must be bonded to several (e.g., eight or more) I/O pins located around the PLD to assure that all sections of Vtt bus 150 are maintained at 3.3V. Therefore, when PCI compliance is required, fewer I/O pins are available for I/O functions, thereby limiting the logic operation that can be implemented on the PLD.
What is needed is an improved low voltage I/O circuit with a high voltage tolerance that avoids the above-mentioned problems associated with the prior art I/O circuits.